1. Field of the Invention
This invention relates generally to the field of semiconductor device manufacturing and, more particularly, to a method and apparatus for controlling etch selectivity.
2. Description of the Related Art
There is a constant drive to reduce the size, or scale, of semiconductor devices, such as transistors, to increase the overall speed of the device incorporating such transistors. A conventional integrated circuit device, such as a microprocessor, is typically comprised of many millions of transistors formed above the surface of a semiconductive substrate.
Many modern integrated circuit devices are very densely packed, i.e., there is very little space between the transistors formed above the substrate. The manufacture of semiconductor devices requires a number of discrete process steps to create a packaged semiconductor device from raw semiconductor material. The various processes include the initial growth of the semiconductor material, the slicing of the semiconductor crystal into individual wafers, the fabrication stages (etching, doping, ion implanting, or the like), and the packaging and final testing of the completed device.
Among the important aspects in semiconductor device manufacturing are rapid thermal annealing (RTA) control, chemical-mechanical polishing (CMP) control, etch control, and overlay control. As technology advances facilitate smaller critical dimensions for semiconductor devices, the need for reduction of errors increases dramatically. Proper formation of sub-sections within a semiconductor device is an important factor in ensuring proper performance of the manufactured semiconductor device. Critical dimensions of the sub-sections generally have to be within a predetermined acceptable margin of error for semiconductor devices to be within acceptable manufacturing quality.
Generally, most features on a semiconductor device are formed by depositing layers of material (e.g., conductive or insulative) and patterning the layers using photolithography and etch processes. There are many variables that affect the accuracy and repeatability of the etch processes used to form the features. One particular etch process involves a plasma etch that removes a portion of an upper layer formed on the wafer. Although the plasma etch is primarily an anisotropic etch, it does have an isotropic component. During the etch, reactants in the plasma form a polymer byproduct that deposits on the surfaces exposed to the plasma, including the features being etched. Polymer that forms on sidewalls of the feature being etched is not removed by the anisotropic component of the etch. Typically, a halocarbon gas (i.e., containing a halogen such as chlorine or fluorine and a hydrocarbon group) is used in the etch process. Ions of hydrocarbon groups are generated in the plasma and accelerated toward the surface of the wafer to perform the anisotropic etch. The anisotropic etch component also removes the polymer buildup on the surfaces perpendicular to the ion flux. Halogenated radicals, also generated in the plasma, have an isotropic chemical etching effect that removes the surface film where the polymer has been “sputtered” away. The isotropic etch component also affects the sidewall surfaces, but to a lesser degree than the more “flat” surfaces.
After the desired layer has been removed, the plasma etch process typically etches the underlying layer to some degree. For example, during the formation of a transistor, a polysilicon layer is formed over a silicon dioxide layer. The polysilicon is subsequently etched using an anisotropic plasma etch to form a transistor gate electrode. The silicon dioxide is also partially etched during the etching of the polysilicon. Similar etching of the underlying layer is also evident in plasma etches of silicon nitride over silicon dioxide, for example. Variations in the incoming thickness of the upper and underlying layers and in the selectivity of the upper and underlying layers to the plasma etch process (i.e., etch rates for the different materials in the upper and underlying layers are different) result in deviations in the post-etch thickness of the underlying layer from a target post-etch thickness. These post-etch thickness deviations, in turn, may cause corresponding variations in the properties of the device and its performance. Minimizing post-etch thickness variations is particularly important in the formation of features such as polysilicon gate electrodes and local interconnect structures.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.